<parts>
    <!-- BANK 0 -->
    <regblock name="SFR0" start="0x00" end="0x0B" >
        <register name="PORTA"   addr="0x05" bits="RA0,RA1,RA2,RA3,RA4,RA5,RA6,RA7"/>
        <register name="PORTB"   addr="0x06" bits="RB0,RB1,RB2,RB3,RB4,RB5,RB6,RB7"/>
        <register name="EEDATA"  addr="0x08" bits=""/>
        <register name="EEADR"   addr="0x09" bits=""/>
        <register name="PCLATH"  addr="0x0A" bits=""/>
        <register name="INTCON"  addr="0x0B" bits="RBIF,INTF,T0IF,RBIE,INTE,T0IE,PEIE,GIE"/>
    </regblock>
    <datablock name="GPR0" start="0x0C" end="0x4F"/>
    
    <!-- BANK 1 -->
    <regblock name="SFR1" start="0x80" end="0x8B">
        <mapped                  addr="0x80" mapto="0x00"/><!-- INDF -->
        <register name="OPTION"  addr="0x81" reset="11111111"
                  bits="PS0,PS1,PS2,PSA,T0SE,T0CS,INTEDG,RBPU"/>
                  
        <mapped                  addr="0x82" mapto="0x02"/><!-- PCL -->
        <mapped                  addr="0x83" mapto="0x03"/><!-- STATUS -->
        <mapped                  addr="0x84" mapto="0x04"/><!-- FSR -->
        <register name="TRISA"   addr="0x85" bits="0-7" reset="11111111"/>
        <register name="TRISB"   addr="0x86" bits="0-7" reset="11111111"/>
        <register name="EECON1"  addr="0x85" bits="RD,WR,WREN,WRERR" />
        <register name="EECON2"  addr="0x86" bits="" />
        <mapped                  addr="0x8A" mapto="0x0A"/><!-- PCLATCH -->
        <mapped                  addr="0x8B" mapto="0x0B"/><!-- INTCON -->
    </regblock>
    <datablock name="GPR1" start="0x8C" end="0xCF" mapto="0x0C"/>
    
</parts>
