<!DOCTYPE SimulIDE>

<mcu name="6520" core="scripted" script="6520_core.js" data="8" inst_cycle="1" clkpin="P2">

    <regblock name="REGs" start="0x00" end="0x07" >
        <register name="ORA"   addr="0x00" />
        <register name="CRA"   addr="0x01"  mask="00111111" bits="CA10,CA11,PRA0,CA20,CA21,CA22,IRQA2,IRQA1"/>
        <register name="ORB"   addr="0x02" />
        <register name="CRB"   addr="0x03"  mask="00111111" bits="CB10,CB11,PRB0,CB20,CB21,CB22,IRQB2,IRQB1"/>
        <register name="DDRA"  addr="0x04" />
        <register name="DDRB"  addr="0x06" />
    </regblock>
    
    <interrupts enable="">
        <interrupt name="IRQA1"  enable="CA10"  flag="IRQA1"  priority="1" />
        <interrupt name="IRQA2"  enable="CA20"  flag="IRQA2"  priority="1" />
        <interrupt name="IRQB1"  enable="CB10"  flag="IRQB1"  priority="1" />
        <interrupt name="IRQB2"  enable="CB20"  flag="IRQB2"  priority="1" />
    </interrupts>
    
    <port name="PORTA" pins="8" outreg="ORA" configregsA="CRA"
                       type="scripted" 
                       script="6520_PA.js">
    </port>
    
    <port name="PORTB" pins="8" >
    </port>
    
    <port name="PORTD" pins="8" >
    </port>
    
    <port name="PORTR" pins="2" >
    </port>
    
    <port name="CPORT0" pins="CA1,CA2,CB1,CB2,CS0,CS1,CS2,RW,IRQA,IRQB,P2" 
                        type="scripted" 
                        script="6520_CP.js"/>
    <intmem name="MemCtrl" 
        addrport="PORTR"
        dataport="PORTD"
        rwpin="RW"
        cshpin="CS1"
        cslpin="CS2"
        clkpin="P2">
    </intmem>
    
</mcu>
