<!DOCTYPE SimulIDE>

<mcu name="6532" core="intmem" script="6532_core.js" data="144" inst_cycle="1" clkpin="P2"
                 addrport="PORTR"
                 dataport="PORTD"
                 rwpin="RW"
                 cshpin="CS1"
                 cslpin="CS2"
                 clkpin="P2">

    <datablock name="RAM" start="0x0000" end="0x007F"/>
    
    <regblock name="REGs" start="0x0080" end="0x008F" offset="0x0080">
        <register name="ORA"   addr="0x00" />
        <register name="DDRA"  addr="0x01" />
        <register name="ORB"   addr="0x02" />
        <register name="DDRB"  addr="0x03" />
        
        <register name="IFR"   addr="0x05"  mask="0" bits="0,0,0,0,0,EXTIF,T0IF"/><!-- INT FLAGS -->
        <register name="IER"   addr="0x06"  mask="0" bits="0,0,0,0,0,EXTIE,T0IE"/><!-- INT ENABLE -->
        <register name="ECR"   addr="0x07"  mask="0" bits="ECR0,ECR1,0,0,0,0,0"/><!-- EDGE CONTROL PA7-->
        
        <register name="ADDR"  addr="0x7F" />
    </regblock>
    
    <interrupts enable="">
        <interrupt name="EXT" enable="EXTIE" flag="EXTIF" pin="IRQ"/>
        <interrupt name="T1"  enable="T1IE"  flag="T1IF"  pin="IRQ"/>
    </interrupts>

    
    <port name="PORTA" pins="8" outreg="ORA" dirreg="DDRA" >
        <!--extint name="EXT" pin="PORTA7" configbits="ECR0,ECR1" -->
    </port>
    
    <port name="PORTB" pins="8" outreg="ORB" dirreg="DDRB">
    </port>
    
    <port name="PORTD" pins="8" >
    </port>
    
    <port name="PORTR" pins="8" >
    </port>
    
    <port name="CPORT0" pins="CS1,CS2,RW,IRQ,P2" />
    
</mcu>
